Some static random access memory (“SRAM”) cell designs may have at least two active elements, one of which may include a Negative Differential Resistance (“NDR”) device. Overall performance of this type of SRAM cell may be based in part upon the properties of the NDR device. A variety of NDR devices have been introduced that include either a bipolar transistor or a quantum-effect device. One advantage of an NDR-based cell for an SRAM design may be its potential for allowing a cell area smaller than conventional SRAM cells.
Recently, thyristors have been introduced by T-RAM Inc. of San Jose, Calif., as a type of NDR device for forming a thyristor-based random access memory device. These types of memories can provide speeds approaching conventional SRAM but with circuit density approaching that of dynamic random access memory (“DRAM”). Moreover, such thyristor-based memory may be integrated within a Complimentary-Metal-Oxide-Semiconductor (“CMOS”) process flow. Such thyristor-based memory may comprise a thin capacitively coupled thyristor (“TCCT”) to form a bi-stable element for an SRAM cell. Additional details regarding a thyristor-based memory device may be found in U.S. Pat. No. 6,767,770 B1, which is incorporated by reference herein in its entirety.
Thyristors may be formed using lateral bipolar transistor technologies as bipolar four-region semiconducting devices, with each region thereof having an alternately n-type or p-type material, for example pnpn. Accordingly, the four regions define three p-n junctions. Terminals, which may be thought of as an anode terminal and a cathode terminal, are used for directing current through the four regions responsive to an input and a control potential. A control terminal, sometimes referred to as a control gate, is selectively capacitively coupled to one of the middle regions responsive to the control potential.
Metal-semiconductor contacts are commonly formed in semiconductor devices by means of a silicide formed as a film of a refractory metal reacted with silicon. Common silicide semiconductor films include but are not limited to metals such as tungsten, titanium, and cobalt. Notably, as used herein, “include” means include without limitation.
An issue with planar transistor fabrication in general, and with the fabrication of thyristor-based devices in particular, is the uniformity of at least some of the silicide features in a given device. With increased non-uniformity in the form of silicide features comes a concomitant increased non-uniformity in current flows between the silicides and one or more of the transistor junctions of the device. This non-uniformity is apparent from device to device within a given die, from die to die within a given wafer, and from wafer to wafer, and has several deleterious results.
FIG. 1 conceptually illustrates some of these silicide non-uniformities. It will be appreciated by those of skill in the art that this figure is solely for illustration of the problems solved herein and does not necessarily reflect the actual fabrication steps or order of fabrication of a given device. In that figure, semiconductor wafer 100 includes a silicon substrate 102 which has formed thereon a layer of buried oxide (“BOx”) 104. A layer of silicon 106 formed over BOx layer 104 is subsequently etched to form a shallow trench isolation feature later filled with isolation oxide 108. The formation of the shallow trench feature and the implementation of isolation oxide 108 define a plurality of silicon rows 205. Silicon rows 205 are doped to form four doped regions, a p+region 116, an n region 118, a p region 120, and an n+ region 122. Separating these regions is a series of junctions 117, 119, and 121. Formed over silicon rows 205 and isolation oxide 108 are first and second nitride spacers, 110 and 112 respectively. Formed between silicon nitride spacers 110 and 112 is a polysilicon gate 114, with dielectric layer 135 providing a gate dielectric between polysilicon gate 114 and region 120. Notably, polysilicon gate 114 is a conductive “stripe” that is substantially orthogonal to a trench substantially filled with isolation oxide 108.
As shown in enlarged section AA, the formation depth of silicide 124 results in an electrical path between silicide 124 and junction 117 of distance “A.” With reference to enlarged section BB, silicide 128 is formed with a distance “B” resulting between junction 121 and silicide 128. Device-to-device non-uniformity in the formation depth and roughness of silicides 124 and 128 result in non-uniformity in distances “A” and “B”, leading to variation in current flow rates between silicide 124 with respect to junction 117 and silicide 128 with respect to junction 121.
A second form of silicide morphology variation which contributes to non-uniform current flow is shown with reference to enlarged section “CC”. This section illustrates silicide depth non-uniformity along the isolation junction where silicide 128 extends generally downward, at 129, along the boundary between doped region 122 and isolation oxide 108. This silicide morphology variation again negatively impacts current density uniformity.
A third form of silicide morphology variation, which contributes to non-uniform current flows, is also shown with reference to enlarged sections “AA” and “BB”. This is the non-uniform lateral encroachment of silicides, for instance silicides 128 and 124 under overlying structures, for instance nitride spacers 110 and 112. This non-uniform lateral encroachment further exacerbates the non-uniform current flow issue previously discussed, by randomly varying the distances “A” and “B” shown in FIG. 1. Additionally, non-uniform lateral encroachment may occur where silicides are formed in gate structures, for instance as at 130, where a silicide 126 formed in gate 114 encroaches under an overlying portion of spacer 110.
These non-uniformities result in increased variations in device performance. As a result, circuits utilizing these devices must be designed robustly to operate properly over a broader range of operating parameters than would otherwise be necessary.
Accordingly, it would be useful and desirable to form one or more of the several silicides of lateral bipolar devices, including thyristor-based memory devices, in a more uniform or repeatable manner. For example, it would be desirable and useful to form a silicide which exhibits one or more of the following characteristics: a substantially more planar lower boundary surface; substantially improved depth repeatability; substantially reduced silicide morphology variation; and substantially reduced or eliminated lateral encroachment.